1. Field of the Invention
The present invention relates to a mask pattern design method and semiconductor manufacturing method, and semiconductor design program, to perform transfer simulation employing design layout data of a mask pattern, and compute yield with verification of the pattern data.
2. Description of the Related Art
In related art, methods to increase layout robustness have been proposed such as a layout optimizer with consideration for manufacturability (DFM: Design For Manufacturing), whereby patterns likely to fail at time of manufacturing during various layout stages, such as standard cells or product chips, are identified, and are corrected to become patterns which can avoid defect, or layouts likely to fail are avoided at time of OPC (Optical Proximity Correction).
Also, feedback is provided to the manufacturing side regarding a method to specify a process to take into particular consideration during process improvements from the defect rate of each layer predicted from the layout, or defects predicted in the layout stage, such as a set in target yield of the product towards the target yield for each process according to the ability as to the defects of the layout.
Such defects occurring in the manufacturing process of a semiconductor integrated circuit include systematic defects which result from the manufacturing process, and random defects which occur spontaneously.
With the mask pattern correcting method in Japanese Unexamined Patent Application Publication No. 2006-154404, a pattern having locations of optical isolation of a semiconductor integrated circuit layout is extracted, and by providing an extension portion extending from the end portion of an adjacent pattern or from the end edge portion, occurrences of an optically isolated pattern can be minimized.
As a result, the process window of the lithography process with the semiconductor integrated circuit manufacturing can be expanded. That is to say, a process margin such as a focus margin or the like during the lithography process can be expanded. Accordingly, in particular, a situation can be avoided wherein during focus fluctuation, necessary contrast cannot be obtained, whereby desired line width cannot be obtained, the line width of the wiring is decreased, resulting in a systematic defect of an open error (so-called Hot Spot) from a broken wire or connection defect.
In Japanese Unexamined Patent Application Publication No. 2006-253409, a proposal has been made to analyze systematic defects resulting from an alignment shift between the wiring and the via occurring in the manufacturing process of the semiconductor integrated circuit from the layout, wherein layout modification is made to double on a via likely to have an error.
In Japanese Unexamined Patent Application Publication No. 2003-41960, the transfer shape on a wafer is computed with multiple process conditions, whereby in the case that the transfer shape does not satisfy the specified dimension allowance values, this is determined to be a Hot Spot, a design layout index for avoiding a Hot Spot is created from the difference amount from the dimension allowance values, and layout modifications are performed.
On the other hand, with random defects, faults such as particles in the manufacturing process cause open wiring, shorted wires, and open holes. With a semiconductor integrated circuit layout, a method to predict random defects is proposed (C. H. Stapper, “Modeling of Integrated Circuit Defect Sensitivities”, IBM J. Res. Develop. USA 1983, November Vol. 27, p. 549-557), such method being to compute yield by employing a critical area that fails when the defective distribution curve and particles falls.
A critical area indicates a ratio of fatal locations in a circuit layout which is opened or shorted out by particles or the like, with the various processes in the manufacturing process. Wire Spreading function during wiring of a chip layout or Via Doubling function to avoid single via defects are provided by a wiring tool, for reduction in random defects by reduction of critical areas.
These layout robustness improvement methods may have a trade-off relation wherein layout correction as to a specified defect cause can lead to another defect. For example, the Hot Spot of the wiring layer can be avoided by employing the method proposed in Japanese Unexamined Patent Application Publication No. 2006-154404, but the critical area of shorted wiring increases (see FIG. 9). Also, with the Via Doubling function, Hot Spots can increase, resulting from combinations of dense and isolated patterns (see FIG. 10).
Thus, by employing a layout robustness method, the above-mentioned trade-offs for yield improvement advantages can be quantitatively considered, and the layout robustness method with the maximum yield can be selected. Also, yield can be predicted for random defects with a method employing critical areas.
On the other hand, with systematic defects occurred in one layer or between multiple layers of a semiconductor integrated circuit resulting from process variability in the lithography process (open wiring, shorted wires, failed via connections, wiring-via shorts, intra-via shorts), process window analysis (the transfer shape on the wafer is predicted in the case that the process from the lithography simulation applying multiple process conditions within a manufacturing process variability allowance value (process window) is uneven is predicted, and whether or not the transfer shape thereof fulfils the dimension allowance values is confirmed) is performed employing lithography simulation (simulation to predict the finished shape on the wafer), whereby in the case that the transfer shape of the specified process parameter condition is not within the dimension allowance values, the occurrence probability of such process condition is decreased by the amount of yield, whereby computing with yield can be performed (Lars Liebmann, “Reducing DfM to Practice: the Lithography Manufacturability Assessor”, Proc. of SPIE, vol. 6156, 2006). With the connection defects between the wiring and via resulting from an alignment shift, computations can be made with a method to express the alignment shift at the layout stage such as that described in Japanese Unexamined Patent Application Publication No. 2006-253409.
With providing defect information predicted at the layout stage to the manufacturing side as feedback, a method to specify a process to focus on process improvements from defect distribution by layer and random yield by layer computed from the critical areas, or setting the target yield of product into each process yield, and so forth are performed.
Also, if the systematic defects become quantifiable in addition to the random yield information feedback, the defects resulting from variability from the manufacturing processing predicted in the layout stage can be anticipated as feedback to the manufacturing side. For example, a layout with high via redundancy rate is a layout which is robust as to alignment shifting, enabling relaxed alignment specifications in a range not influencing the yield, and decrease in the rate of rework of wafers. Conversely, in the event that connection defects occur in the range of combined specifications, the device management specifications for an alignment wherein yield does not decline is defined, enabling feedback to the process control.